FIG. 1 is a sectional view illustrating an example of a conventional high voltage semiconductor device.
Referring to FIG. 1, an n-type drift region 110 is disposed at a predetermined region on a p-type semiconductor substrate 110. An n+-type source region 121 is disposed on the surface of semiconductor substrate 100, and spaced apart from n-type drift region 110 at a predetermined interval. An n+-type drain region 122 is disposed on n-type drift region 110. A channel region 102 is disposed on the surface of semiconductor substrate 100 between n-type drift region 100 and n+-type source region 121, and an inversion layer is formed in channel region 102 under a predetermined condition. A local oxidation of silicon (LOCOS) field plate 130 is disposed on n-type drift region 110 between channel region 102 and n+-type drain region 122.
A gate electrode layer 150 is disposed above channel region 102, where a gate insulating layer 140 is interposed therebetween. Gate electrode layer 150 extends to the top surface of field plate 130 on n-drift region 110. Gate spacer layers 160 are formed at both sidewalls of gate electrode layer 150. n+-type source region 121, n+-type drain region 122, and gate electrode layer 150 are respectively connected to a source terminal S, a drain terminal D, and a gate terminal G through their interconnection structures.
In the aforementioned high voltage semiconductor device, to secure a breakdown voltage (BV), n-type drift region 110 is required, and the length of channel needs to be long. n-type drift region 110 and the long channel occupy a majority of surface area of the high voltage semiconductor device. Moreover, when field plate 130 is employed, a current passing path is formed in n-type drift region 110, along the bottom surface of field plate 130, as indicated by an arrow in FIG. 1. Accordingly, the relatively lengthened current path and the increased ON-resistance (Ron) of the semiconductor device deteriorate the operation performance of the semiconductor device.